To prevent damage to the entire device resulting from electrostatic discharge (ESD) stress, ESD protection circuits are typically coupled to input/output (I/O) terminals or bonding pads or the circuits are positioned in devices susceptible to ESD damage during normal operation of an integrated circuit (IC).
FIG. 1 illustrates a cross-section of a conventional field transistor used for ESD protection. As illustrated in FIG. 1, a p+-type bottom region 12 and a p-type well region 13 are sequentially formed on a p-type substrate 11. The impurity concentration of the p+-type bottom region 12 is higher than that of the p-type well region 13. An n+-type source region 14 and an n+-type drain region 15 are formed in the p-type well region 13 so that regions 14 and 15 are spaced apart from each other by a distance corresponding to a region for forming an inversion layer. A p+-type diffusion region 16 is also formed in the p-type well region 13 so that it is spaced apart from the n+-type source region 14 by a predetermined distance. The p+-type diffusion region 16 is provided for applying bias to the p-type well region 13. A field oxide layer 17 is formed on the p-type well region 13 between the p+-type diffusion region 16 and the n+-type source region 14 and between the n+-type source region 14 and the n+-type drain region 15.
A patterned gate conductive layer 18 is formed on a gate insulating layer 19 and a field oxide layer 17. The gate conductive layer 18 is patterned to overlap parts of the n+-type source region 14 and the n+-type drain region 15 while overlapping all of field oxide layer 17. A gate electrode 20 is formed on the patterned gate conductive layer 18. A source electrode 21 is formed so as to contact the n+-type source region 14 and the p+-type diffusion region 16. A drain electrode 22, which contacts the n+-type drain region 15, is connected to the gate electrode 20 in order to apply a turn-on voltage to the gate electrode 20 when ESD stress from the outside is generated through the drain electrode 22. Interlayer dielectric layer 23 is formed and patterned to electrically isolate each electrode.
In the conventional field transistor represented in FIG. 1, when ESD stress from the outside is generated through the drain electrode 22, a turn-on voltage is applied to the gate electrode 20 to form an inversion layer between the n+-type source region 14 and n+-type drain region 15. The inversion layer provides a complete current path between a drain terminal and a bulk. Thus, ESD current is routed to the bulk through the n+-type drain region 15, the inversion layer, the n+-type source region 14, and the p+-type diffusion region 16, thereby protecting the devices against the ESD stress.
As depicted in FIG. 1, a gate insulating layer 19 is formed between each of the n+-type source region 14 and the n+-type drain region 15 and the gate insulating layer 18 and is significantly thinner than the field oxide layer 17. This smaller thickness increases the possibility of the breakdown of the gate insulating layer 19 due to the ESD stress, significantly reducing the reliability of the device. Such a problem may be solved in two ways. A first way is to make gate insulating layer 19 as thick as the field oxide layer 17. A second way is to form gate conductive layer 18 only on the field oxide layer 17.
The first method is unsatisfactory not only because the manufacturing cost is high, but also the manufacturing process is complicated because of the large number of process steps required by the addition of a mask. The second method is also unsatisfactory in that the n+-type source region 14 and the n+-type drain region 15 are not overlapped by the gate conductive layer 18. Thus, even if the inversion layer is formed between the n+-type source region 14 and the n+-type drain region 15, the inversion layer is not connected to the source region 14 and drain region 15 and does not providing a complete current path between both regions 14 and 15.